Cpri Enhancements - Altera Cyclone V Device Handbook

4-32

CPRI Enhancements

• For a 9-channel device, you can implement a maximum of 4 full duplex 6.144-Gbps CPRI-compliant
channels.
• For a 12-channel device, you can implement a maximum of 6 full duplex 6.144-Gbps CPRI-compliant
channels.
You must increase the voltage on VCCE_GXB and VCCL_GXB to 1.2 V to support the maximum number
of channels.
The reference clock frequency for the 6.144 Gbps CPRI channel must be ≥ 307.2 MHz.
The maximum number of transceiver channels in a Cyclone V GT device that can achieve 6.144-Gbps CPRI
compliance is based on:
• Transceiver performance in meeting the TX jitter specification for 6.144-Gbps CPRI.
• CPRI channels with an auto-rate negotiation capability from 1228.8 Mbps to 6.144 Gbps.
• 6.144-Gbps CPRI channel restriction based on the following figure.
Figure 4-31: 6.144-Gbps CPRI Channel Placement Restriction
The channels next to a PCIe Hard IP block are not timing optimized for the 6.144-Gbps CPRI data rate.
Affected channels are shaded in gray in the above figure. Avoid placing the 6.144-Gbps CPRI channels in
the affected channels. The affected channels can still be used as a CMU for the CPRI channels.
Related Information
Transceiver Architecture in Cyclone V Devices
CPRI Enhancements
The deterministic latency state machine in the word aligner reduces the known delay variation from the
word alignment process and automatically synchronizes and aligns the word boundary by slipping a clock
cycle in the deserializer. Incoming data to the word aligner is aligned to the boundary of the word alignment
Altera Corporation
Transceiver Protocol Configurations in Cyclone V Devices
CV-53004
2013.10.17
Send Feedback