Altera Cyclone V Device Handbook page 25

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CV-52002
2013.05.06
Output Mode
"constrained don't care"
Figure 2-3: Mixed-Port Read-During-Write: New Data Mode
This figure shows a sample functional waveform of mixed-port read-during-write behavior for the "new
data" mode.
Figure 2-4: Mixed-Port Read-During-Write: Old Data Mode
This figure shows a sample functional waveform of mixed-port read-during-write behavior for the "old data"
mode.
Embedded Memory Blocks in Cyclone V Devices
Send Feedback
Memory Type
MLAB
clk_a&b
wren_a
address_a
data_a
AAAA
byteena_a
rden_b
address_b
q_b (registered)
XXXX
clk_a&b
wren_a
address_a
data_a
AAAA
byteena_a
rden_b
address_b
q_b (asynch)
A0 (old data)
Mixed-Port Read-During-Write Mode
The RAM outputs "don't care" or "unknown" value. The
Quartus II software analyzes the timing between write and
read operations in the MLAB.
A0
A1
BBBB
CCCC
DDDD
EEEE
11
A0
A1
AAAA
BBBB
CCCC
A0
BBBB
CCCC
DDDD
11
A0
AAAA
BBBB
A1 (old data)
Description
FFFF
DDDD
EEEE
FFFF
A1
EEEE
FFFF
A1
DDDD
EEEE
Altera Corporation
2-5

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