I 2 C Controller; Features Of The I 2 C Controller - Altera Cyclone V Device Handbook

2013.12.30
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2
The I C controller provides support for a communication link between integrated circuits on a board. It is
a simple two-wire bus which consists of a serial data line (SDA) and a serial clock (SCL) for use in applications
such as temperature sensors and voltage level translators to EEPROMs, A/D and D/A converters, CODECs,
and many types of microprocessors. †
The hard processor system (HPS) provides four I
2
serially with I C buses. Each I
of up to 100 Kbps or fast mode of up to 400 Kbps. These I
®
DesignWare APB I
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Each I C controller must be programmed to operate in either master or slave mode only. Operating as a
master and slave simultaneously is not supported. †
Note: Portions
are registered trademarks of Synopsys, Inc. All documentation is provided "as is" and without any
warranty. Synopsys expressly disclaims any and all warranties, express, implied, or otherwise, including
the implied warranties of merchantability, fitness for a particular purpose, and non-infringement,
and any warranties arising out of a course of dealing or usage of trade.
†Paragraphs marked with the dagger (†) symbol are Synopsys Proprietary. Used with permission.
Features of the I
2
The I C controller has the following features:
• Maximum clock speed of up to 400 Kbps
• One of the following I
• A master in an I
• A slave in an I
• 7- or 10-bit addressing †
• Mixed read and write combined-format transactions in both 7-bit and 10-bit addressing mode †
• Bulk transmit mode †
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2
C controller can operate in master or slave mode, and support standard mode
2
C (DW_apb_i2c) controller.
©
2013 Synopsys, Inc. Used with permission. All rights reserved. Synopsys & DesignWare
2
C Controller
2
C operations:
2
C system and programmed only as a master †
2
C system and programmed only as a slave †
2
I C Controller
2
C controllers to enable system software to communicate
2
C controllers are instances of the Synopsys
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®
ISO
9001:2008
Registered