Address Remapping - Altera Cyclone V Device Handbook

cv_54004
2013.12.30
NAND
SD/MMC
ETR
DAP

Address Remapping

The interconnect supports address remapping through the remap register. Remapping allows software to
control which memory device (SDRAM, on-chip RAM, or boot ROM) is accessible at address 0x0 and the
accessibility of the HPS-to-FPGA and lightweight HPS-to-FPGA bridges. The remap register is one of the
NIC-301 Global Programmers View (GPV) registers and maps into the address space of the following L3
masters:
• MPU
• FPGA-to-HPS bridge
• DAP
The remapping bits in the remap register are not mutually exclusive. The lowest order remap bit has higher
priority when multiple slaves are remapped to the same address. Each bit allows different combinations of
address maps to be formed. There is only one remapping register available in the GPV, so modifying the
remap register affects all memory maps of all the masters of the interconnect.
Interconnect
Send Feedback
Masters Connected Slaves
• HPS-to-FPGA Bridge
• ACP ID Mapper Data
• On-Chip RAM
• SDRAM Controller Subsystem L3 Data
• HPS-to-FPGA Bridge
• ACP ID Mapper Data
• On-Chip RAM
• SDRAM Controller Subsystem L3 Data
• HPS-to-FPGA Bridge
• On-Chip RAM
• SDRAM Controller Subsystem L3 Data
• L4 SP Bus Slaves
• L4 MP Bus Slaves
• L4 OSC1 Bus Slaves
• L4 MAIN Bus Slaves
• L4 SPIM Bus Slaves
• Lightweight HPS-to-FPGA Bridge
• USB OTG 0/1 CSR
• NAND CSR
• NAND Command and Data
• Quad SPI Flash Data
• FPGA Manager
• HPS-to-FPGA Bridge
• ACP ID Mapper Data
• On-Chip RAM
• SDRAM Controller Subsystem L3 Data
4-9
Address Remapping
Altera Corporation