Altera Cyclone V Device Handbook page 148

CV-52005
2014.01.10
You can modify the three-resistor network values to reduce power or improve the noise margin. Choose
resistor values that satisfy the following equation.
Figure 5-26: Resistor Network Calculation
Note: Altera recommends that you perform additional simulations with IBIS or SPICE models to validate
that the custom resistor values meet the RSDS or mini-LVDS I/O standard requirements.
For information about the data rates supported for external single resistor or three-resistor network, refer
to the device datasheet.
Related Information
Cyclone V Device Datasheet
National Semiconductor (www.national.com)
For more information about the RSDS I/O standard, refer to the RSDS Specification on the National
Semiconductor web site.
LVPECL Termination
The Cyclone V devices support the LVPECL I/O standard on input clock pins only:
LVPECL input operation is supported using LVDS input buffers.
LVPECL output operation is not supported.
Use AC coupling if the LVPECL common-mode voltage of the output buffer does not match the LVPECL
input common-mode voltage.
Note: Altera recommends that you use IBIS models to verify your LVPECL AC/DC-coupled termination.
Figure 5-27: LVPECL AC-Coupled Termination
Support for DC-coupled LVPECL is available if the LVPECL output common mode voltage is within the
Cyclone V LVPECL input buffer specification.
I/O Features in Cyclone V Devices
Send Feedback
LVPECL
Output Buffer
0.1 µF
Z = 50 Ω
0
0.1 µF
Z = 50 Ω
0
LVPECL
Input Buffer
V
ICM
50 Ω
50 Ω
5-51
LVPECL Termination
Altera Corporation