Receiver Clocking - Altera Cyclone V Device Handbook

2-14

Receiver Clocking

Note: When a channel PLL is configured as a CMU PLL to drive the local clock divider or the central clock
divider of its own channel, the channel PLL cannot be used as a CDR. Without a CDR, the channel
can be used only as a transmitter.
Receiver Clocking
This section describes receiver clocking, which is the clocking architecture internal to the receiver channel
of a transceiver.
Figure 2-12: Clocking Architecture for Receiver PCS and PMA Configuration
Receiver PMA
Parallel Clock
(Recovered)
Input
Reference
Clock
The CDR in the PMA of each channel recovers the serial clock from the incoming data and generates the
parallel clock (recovered) by dividing the serial clock (recovered). The deserializer uses both clocks. The
receiver PCS can use the following clocks depending on the configuration of the receiver channel:
• Parallel clock (recovered) from the CDR in the PMA
• Parallel clock from the clock divider that is used by the channel's transmitter PCS
Table 2-8: Clock Sources for All Receiver PCS Blocks
Block
Word aligner
Rate match FIFO
8B/10B decoder
Byte deserializer
Byte ordering
Altera Corporation
Receiver PCS
Parallel Clock (from the Clock Divider)
Data Path
Serial Clock
Parallel Clock
Side
- Parallel clock (recovered)
Write Parallel clock (recovered)
Read Parallel clock from the clock divider
- • Rate match FIFO is not used-Parallel clock (recovered)
• Rate match FIFO is used-Parallel clock from the clock
divider
Write • Rate match FIFO is not used-Parallel clock (recovered)
• Rate match FIFO is used-Parallel clock from the clock
divider
Read Divided down version of the write side clock depending on
the deserialization factor of 1 or 2, also called the parallel
clock (divided)
- Parallel clock (divided)
/2
Clock Source
Transceiver Clocking in Cyclone V Devices
CV-53002
2013.05.06
FPGA Fabric
rx_parallel_data
rx_coreclkin /
rx_std_coreclkin
rx_clkout /
rx_std_clkout
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