Altera Cyclone V Device Handbook page 327

1-40
Word Aligner Operations in Deterministic Latency State Machine Mode
synchronization code groups that the link must receive to acquire synchronization and a specific number
of erroneous code groups that it must receive to fall out of synchronization.
In PCIe configurations, the word aligner in automatic synchronization state machine mode automatically
selects the word alignment pattern length and pattern as specified by each protocol. The synchronization
state machine parameters are fixed for PCIe configurations as specified by the respective protocol.
Table 1-22: Word Aligner in Synchronization State Machine Modes for a PCIe Configuration
Number of valid synchronization code groups or ordered sets received to achieve synchro-
nization
Number of erroneous code groups received to lose synchronization
Number of continuous good code groups received to reduce the error count by one
After deassertion of the reset_rx_digital signal in automatic synchronization state machine mode,
the word aligner starts looking for the word alignment pattern or synchronization code groups in the received
data stream. When the programmed number of valid synchronization code groups or ordered sets is received,
the rx_syncstatus status bit is driven high to indicate that synchronization is acquired. The
rx_syncstatus status bit is constantly driven high until the programmed number of erroneous code
groups is received without receiving intermediate good groups; after which rx_syncstatus is driven
low. The word aligner indicates loss of synchronization (rx_syncstatus remains low) until the
programmed number of valid synchronization code groups are received again.
Word Aligner Operations in Deterministic Latency State Machine Mode
In deterministic latency state machine mode, word alignment is achieved by performing a clock-slip in the
deserializer until the deserialized data coming into the receiver PCS is word-aligned. The deterministic
latency state machine controls the clock-slip process in the deserializer after the word aligner has found the
alignment pattern and has identified the word boundary. Deterministic latency state machine mode offers
a reduced latency uncertainty in the word alignment operation for applications that require deterministic
latency.
Table 1-23: Word Aligner Operations in Deterministic Latency State Machine Mode
PCS Mode
Single Width
Double Width
Altera Corporation
Mode
PMA PCS Interface
Width
10 bits 1. After the rx_digitalreset signal deasserts, a 0-to-1
20 bits
2. After the pattern is found and the word boundary is
3. When clock-slip is complete, the deserialized data coming
Word Alignment Operation
transition in the rx_enapatternalign register
triggers the word aligner to look for the predefined word
alignment pattern, or its complement, in the received data
stream.
identified, the state machine controls the deserializer to
clock-slip the boundary-indicated number of serial bits.
into the receiver PCS is word-aligned and indicated when
the rx_syncstatus signal asserts.
Transceiver Architecture in Cyclone V Devices
CV-53001
2013.05.06
PCIe
4
17
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