Interleaving Options - Altera Cyclone V Device Handbook

cv_54008
2013.12.30
Controller ECC
Controller ECC provides the following features:
• Byte writes The memory controller performs a read-modify-write operation to ensure that the ECC
data remains valid when a subset of the bits of a word is being written. If an entire word is being written
(but less than a full burst) and the DM pins are connected, no read is necessary and only that word is
updated. If controller ECC is disabled, byte-writes have no performance impact.
• ECC write backs When a read operation detects a correctable error, the memory location is scheduled
for a read-modify-write operation to correct the single-bit error. ECC write backs are enabled and disabled
through the cfg_enable_ecc_code_overwrites field in the ctrlcfg register.
• Notification of ECC errors The memory controller provides interrupts for single-bit and double-bit
errors. The status of interrupts and errors are recorded in status registers, as follows:
• The dramsts register records interrupt status.
• The dramintr register records interrupt masks.
• The sbecount register records the single-bit error count.
• The dbecount register records the double-bit error count.
• The erraddr register records the address of the most recent error.
Byte Writes
Byte writes with ECC enabled are executed as a read-modify-write. Typical operations only use a single entry
in the timer bank pool. Controller ECC enabled sub-word writes use two entries. The first operation is a
read and the second operation is a write. These two operations are transferred to the timer bank pool with
an address dependency so that the write cannot be performed until the read data has returned. This approach
ensures that any subsequent operations to the same address (from the same port) are executed after the write
operation, because they are ordered on the row list after the write operation.
If an entire word is being written (but less than a full burst), then no read is necessary and only that word is
updated.
ECC Write Backs
If the controller ECC is enabled and a read operation results in a correctable ECC error, the controller
corrects the location in memory, if write backs are enabled. The correction results in scheduling a new read-
modify-write. A new read is performed at the location to ensure that a write operation modifying the location
is not overwritten. The actual ECC correction operation is performed as a read-modify-write operation.
User Notification of ECC Errors
When an ECC error occurs, an interrupt signal notifies the MPU subsystem, and the ECC error information
is stored in the status registers.

Interleaving Options

The controller supports the following address-interleaving options:
• Noninterleaved
• Bank interleave without chip select interleave
• Bank interleave with chip select interleave
SDRAM Controller Subsystem
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Controller ECC
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