Channel Bonding; Pll Sharing; Document Revision History - Altera Cyclone V Device Handbook

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2013.05.06
Registered Mode
To eliminate the FIFO latency uncertainty for applications with stringent datapath latency uncertainty
requirements, bypass the FIFO functionality in registered mode to incur only one clock cycle of datapath
latency when interfacing the transmitter channel to the FPGA fabric. Configure the FIFO to registered mode
when interfacing the transmitter channel to the FPGA fabric or PCIe hard IP block to reduce datapath
latency. In registered mode, the low-speed parallel clock that is used in the transmitter PCS clocks the FIFO.

Channel Bonding

The high-speed serial clock and low-speed parallel clock skew between channels and unequal latency in the
transmitter phase compensation FIFO contribute to transmitter channel-to-channel skew. Bonded transmitter
datapath clocking provides low channel-to-channel skew when compared with non-bonded channel
configurations.
• Bonded channel configurations—the serial clock and parallel clock for all bonded channels are generated
by the transmit PLL and central clock divider, resulting in lower channel-to-channel clock skew.
The transmitter phase compensation FIFO in all bonded channels share common pointers and control
logic generated in the central clock divider, resulting in equal latency in the transmitter phase
compensation FIFO of all bonded channels. The lower transceiver clock skew and equal latency in the
transmitter phase compensation FIFOs in all channels provide lower channel-to-channel skew in bonded
channel configurations.
• Non-bonded channel configurations—the parallel clock in each channel are generated independently by
its local clock divider, resulting in higher channel-to-channel clock skew.
The transmitter phase compensation FIFO in each non-bonded channel has its own pointers and control
logic that can result in unequal latency in the transmitter phase compensation FIFO of each channel. The
higher transceiver clock skew and unequal latency in the transmitter phase compensation FIFO in each
channel can result in higher channel-to-channel skew.
Related Information
Transceiver Clocking in Cyclone V Devices

PLL Sharing

In a Quartus II design, you can merge two different protocol configurations to share the same CMU PLL
resources. These configurations must fit in the same transceiver bank and the input refclk and PLL output
frequencies must be identical.

Document Revision History

The revision history for this chapter.
Transceiver Architecture in Cyclone V Devices
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Registered Mode
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