Altera Cyclone V Device Handbook page 163

5-66
Data Realignment Block (Bit Slip)
Figure 5-38: Receiver Block Diagram
10 bits
maxiumum
data width
Data Realignment Block (Bit Slip)
Skew in the transmitted data along with skew added by the link causes channel-to-channel skew on the
received serial data streams. To compensate for this channel-to-channel skew and establish the correct
received word boundary at each channel, each receiver channel has a dedicated data realignment circuit that
realigns the data by inserting bit latencies into the serial stream.
An optional
RX_CHANNEL_DATA_ALIGN
from the internal logic. The data slips one bit on the rising edge of
for the
RX_CHANNEL_DATA_ALIGN
The minimum pulse width is one period of the parallel clock in the logic array.
The minimum low time between pulses is one period of the parallel clock.
The signal is an edge-triggered signal.
The valid data is available two parallel clock cycles after the rising edge of
Figure 5-39: Data Realignment Timing
This figure shows receiver output (
The data realignment circuit can have up to 11 bit-times of insertion before a rollover occurs. The
programmable bit rollover point can be from 1 to 11 bit-times, independent of the deserialization factor.
Set the programmable bit rollover point equal to, or greater than, the deserialization factor—allowing enough
depth in the word alignment circuit to slip through a full word. You can set the value of the bit rollover point
using the MegaWizard Plug-In Manager. An optional status port,
fabric from each channel to indicate the reaching of the preset rollover point.
Altera Corporation
IOE supports SDR, DDR, or non-registered datapath
2
10
rx_out
Deserializer
10
DOUT
FPGA
Fabric
rx_outclock
LVDS Clock Domain
port controls the bit insertion of each receiver independently controlled
signal include the following items:
) after one bit slip pulse with the deserialization factor set to 4.
RX_OUT
rx_inclock
3
rx_in
rx_outclock
rx_channel_data_align
rx_out
IOE
Bit Slip
DIN DOUT DIN
diffioclk
2
(LOAD_EN,
diffioclk)
3 (LVDS_LOAD_EN,
LVDS_diffioclk, rx_outclock)
Fractional PLL
RX_CHANNEL_DATA_ALIGN
2 1 0 3 2 1 0 3
3210 321x
RX_CDA_MAX
LVDS Receiver
+ rx_in
–
rx_inclock / tx_inclock
. The requirements
RX_CHANNEL_DATA_ALIGN
2 1 0
xx21 0321
, is available to the FPGA
I/O Features in Cyclone V Devices
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CV-52005
2014.01.10
.