Pcs Architecture - Altera Cyclone V Device Handbook

CV-53001
2013.05.06

PCS Architecture

Figure 1-21: PCS Block Diagram of a Transceiver Channel in a Cyclone V Device
The serial and parallel clocks are sourced from the clock divider.
Transmitter PMA
Serial
Clock
Receiver PMA
Parallel Clock
The transceiver channel PCS datapath is categorized into two configurations—single-width and double-
width, based on the transceiver channel PMA-PCS width (or serialization/deserialization factor).
Table 1-10: PCS Datapath Configurations
Parameters
PMA PCS Interface Width
FPGA Fabric Transceiver Interface
Width
(2)
The byte serializer and deserializer are enabled.
Transceiver Architecture in Cyclone V Devices
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Transmitter PCS
Receiver PCS
Recovered Clock
from Master Channel
8 or 10 bit
8 or 10 bit
16 or 20 bit
Single-Width
16 or 20 bit
16 or 20 bit
(2)
32 or 40 bit
PCS Architecture
/2
/2
Double-Width
(2)
Altera Corporation
1-27
Cyclone V
FPGA Fabric
tx_parallel data
tx_coreclkin
tx_clkout
rx_parallel data
rx_coreclkin
rx_clkout
Serial Clock
Parallel Clock