Altera Cyclone V Device Handbook page 948

cv_54019
2013.12.30
Here the number of data items to be transferred in a DMA burst is equal to the empty space in the transmit
FIFO buffer. Consider the following two different watermark level settings. †
• Case 1: DMATDLR = 64: †
• Transmit FIFO watermark level = DMATDLR = 64: †
• DMA burst length = FIFO_DEPTH - DMATDLR = 192: †
• SPI transmit FIFO_DEPTH = 256: †
• Block transaction size = 960: †
Figure 19-14: Transmit FIFO Watermark Level = 64
The number of burst transactions needed equals the block size divided by the number of data items per
burst:
Block transaction size/DMA burst length = 960/192 = 5
The number of burst transactions in the DMA block transfer is 5. But the watermark level, DMATDLR, is
quite low. Therefore, the probability of transmit underflow is high where the SPI serial transmit line needs
to transmit data, but there is no data left in the transmit FIFO buffer. This occurs because the DMA has not
had time to service the DMA request before the FIFO buffer becomes empty.
• Case 2: DMATDLR = 192†
• Transmit FIFO watermark level = D MATDLR = 192 †
• DMA burst length = FIFO_DEPTH - DMATDLR = 64 †
• SPI transmit FIFO_DEPTH = 256 †
• Block transaction size = 960 †
Figure 19-15: Transmit FIFO Watermark Level = 192
Number of burst transactions in block: †
Block transaction size/DMA burst length = 960/64 = 15 †
SPI Controller
Send Feedback
FIFO_DEPTH = 256
Transmit FIFO
Watermark Level
Data Out
FIFO_DEPTH = 256
Transmit FIFO
Watermark Level
Data Out
Transmit
FIFO Buffer
FIFO_DEPTH - DMATDLR = 192
Empty
DMATDLR = 64
Full
Transmit
FIFO Buffer
Empty
FIFO_DEPTH - DMATDLR = 64
Full
DMATDLR = 192
Transmit Watermark Level
Data In
DMA
Controller
Data In
DMA
Controller
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