Altera Cyclone V Device Handbook page 880

cv_54017
2013.12.30
As transmission starts, the First Descriptor must have (TDES1[29]) set. When this occurs, frame data transfers
from the Host buffer to the MTL transmit FIFO buffer. Concurrently, if the current frame has the Last
Descriptor (TDES1[30]) clear, the transmit Process attempts to acquire the Next descriptor. The transmit
Process expects this descriptor to have TDES1[29] clear. If TDES1[30] is clear, it indicates an intermediary
buffer. If TDES1[30] is set, it indicates the last buffer of the frame. †
After the last buffer of the frame has been transmitted, the DMA writes back the final status information to
the Transmit Descriptor 0 (TDES0) word of the descriptor that has the last segment set in Transmit Descriptor
1 (TDES1[30]). At this time, if Interrupt on Completion (TDES1[31]) is set, the Bit 0 (Transmit Interrupt)
of Register 5 (Status Register) is set, the Next descriptor is fetched, and the process repeats. †
The actual frame transmission begins after the MTL transmit FIFO buffer has reached either a programmable
transmit threshold (Bits [16:14] of Register 6 (Operation Mode Register)), or a full frame is contained in the
FIFO buffer. There is also an option for Store and Forward Mode (Bit 21 of Register 6 (Operation Mode
Register)). Descriptors are released (Own bit TDES0[31] clears) when the DMA finishes transferring the
frame. †
Note: To ensure proper transmission of a frame and the next frame, you must specify a non-zero buffer
size for the transmit descriptor that has the Last Descriptor (TDES1[30]) set. †
Transmit Polling Suspended
Transmit polling can be suspended by either of the following conditions: †
• The DMA detects a descriptor owned by the Host (TDES0[31]=0). To resume, the driver must give
descriptor ownership to the DMA and then issue a Poll Demand command. †
• A frame transmission is aborted when a transmit error because of underflow is detected. The appropriate
Transmit Descriptor 0 (TDES0) bit is set. †
If the DMA goes into SUSPEND state because of the first condition, then both Bit 16 (Normal Interrupt
Summary) and Bit 2 (Transmit Buffer Unavailable) of Register 5 (Status Register) are set. If the second
condition occur, both Bit 15 (Abnormal Interrupt Summary) and Bit 5 (Transmit Underflow) of Register 5
(Status Register) are set, and the information is written to Transmit Descriptor 0, causing the suspension. †
In both cases, the position in the transmit List is retained. The retained position is that of the descriptor
following the Last descriptor closed by the DMA. †
The driver must explicitly issue a Transmit Poll Demand command after rectifying the suspension cause. †
Reception
Receive functions use receive descriptors.
The receive DMA engine's reception sequence is depicted proceeds as follows:
1. The host sets up receive descriptors (RDES0-RDES3) and sets the Own bit (RDES0[31]).
2. When Bit 1 (SR) of Register 6 (Operation Mode Register) is set, the DMA enters the Run state. While in
the Run state, the DMA polls the receive descriptor list, attempting to acquire free descriptors. If the
fetched descriptor is not free (is owned by the host), the DMA enters the Suspend state and jumps to
†
step 9.
3. The DMA decodes the receive data buffer address from the acquired descriptors.
4. Incoming frames are processed and placed in the acquired descriptor's data buffers.
5. When the buffer is full or the frame transfer is complete, the receive engine fetches the next descriptor.
6. If the current frame transfer is complete, the DMA proceeds to
next fetched descriptor and the frame transfer is not complete (EOF is not yet transferred), the DMA
sets the Descriptor Error bit in the RDES0 (unless flushing is disabled in Bit 24 of Register 6 (Operation
Ethernet Media Access Controller
Send Feedback
Transmit Polling Suspended
†
†
step 7. If the DMA does not own the
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†
†