Altera Cyclone V Device Handbook page 478

2-4
Dividers
The SDRAM PLL has the following additional feature:
• Phase shift of 1/8 per step
• Phase shift range is 0 to 7
FREF, FVCO, and FOUT Equations
FREF = FIN / N
FVCO = FREF
FOUT = FVCO / (Ci
where:
1. FVCO = VCO frequency.
2. FIN = input frequency.
3. FREF = reference frequency.
4. M = numerator, part of the clock feedback path.
5. N = denominator, part of the input clock reference path.
6. Ci = post-scale counter, where i is 0-5 for each of the six counters.
7. K is an internal post-scale counter in the main PLL, where K = 2 for C0, and K = 4 for C1 and C2. K = 1
for C3, C4, and C5 in the main PLL and for all Ci counters in the peripheral and SDRAM PLLs.
Figure 2-2: PLL Block Diagram
Values listed for M, N, and C are actually one greater than the values stored in the CSRs.
F
IN
PLL Bypass Path
Related Information
Cyclone V Device Datasheet
Minimum and maximum VCO frequencies for the main, peripheral, and SDRAM PLLs vary by device speed
grade. For specific details, refer the Cyclone V Device Datasheet.
Dividers
Dividers subdivide the C0-C5 clocks produced by the PLL to lower frequencies. The main PLL C0-C2 clocks
have an additional internal post-scale counter.
Altera Corporation
M = FIN M/N
K) = FREF
F
REF
N
PFD VCO
(1 - 64)
F
FB
M
(1 - 4096)
M/ (Ci K) = (FIN
(1)
F
VCO
Phase Shift C0 Divide
(1/8 Per Step) (1 - 512) × K
Phase Shift C1 Divide
(1/8 Per Step) (1 - 512) × K
Phase Shift C2 Divide
(1/8 Per Step) (1 - 512) × K
Phase Shift C3 Divide
(1/8 Per Step) (1 - 512)
Phase Shift C4 Divide
(1/8 Per Step) (1 - 512)
Phase Shift C5 Divide
(1/8 Per Step) (1 - 512)
M)/ (N
(2)
F
OUT
0
CLKOUT0
1
F
OUT
0
CLKOUT1
1
F
OUT
0
CLKOUT2
1
F
OUT
0
CLKOUT3
1
F
OUT
0
CLKOUT4
1
F
OUT
0
CLKOUT5
1
Bypass
Multiplexer
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2013.12.30
Ci K)
Clock Manager