Write Protection; Data Slave Sequential Access Detection; Clocks; Resets - Altera Cyclone V Device Handbook

cv_54012
2013.12.30
Related Information
XIP Mode Operations

Write Protection

You can program the controller to write protect a specific region of the flash device. The protected region
is defined as a set of blocks, specified by a starting and ending block. Writing to an area of protected flash
region memory generates an error and triggers an interrupt.
You define the block size by specifying the number of bytes per block through the number of bytes per block
field (bytespersubsector) of the device size register (devsz). The lower write protection register
(lowwrprot) specifies the first flash block in the protected region. The upper write protection register
(uppwrprot) specifies the last flash block in the protected region.
The write protection enable bit (en) of the write protection register (wrprot) enables and disables write
protection. The write protection inversion bit (inv) of the wrprot register flips the definition of protection
so that the region specified by lowwrprt and uppwrprt is unprotected and all flash memory outside
that region is protected.

Data Slave Sequential Access Detection

The quad SPI flash controller detects sequential accesses to the data slave interface by comparing the current
access with the previous access. An access is sequential when it meets the following conditions:
• The address of the current access sequentially follows the address of the previous access.
• The direction of the current access (read or write) is the same as previous access.
• The size of the current access (byte, half-word, or word) is the same as previous access.
When the access is detected as nonsequential, the sequential access to the flash device is terminated and a
new sequential access begins. Altera recommends accessing the data slave sequentially. Sequential access
has less command overhead, and therefore, increases data throughput.

Clocks

There are two clock inputs to the quad SPI controller (l4_mp_clk and l4_main_clk) and one clock
output (sclk_out). The quad SPI flash controller uses the l4_mp_clk clock to clock the data slave
transfers and register slave accesses. The l4_main_clk clock is the reference clock for the quad SPI
controller and is used to serialize the data and drive the external SPI interface. The sclk_out clock is the
clock source for the connected flash devices.
The l4_main_clk clock must be greater than two times the l4_mp_clk. The sclk_out clock is derived
by dividing down the l4_main_clk clock by the baud rate divisor field (bauddiv) of the cfg register.
Related Information
Clock Manager

Resets

A single reset signal (qspi_flash_rst_n) is provided as an input to the quad SPI controller. The reset
manager drives the signal on a cold or warm reset.
Related Information
Reset Manager
Quad SPI Flash Controller
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Write Protection
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