Reduced .Mif Reconfiguration; Unsupported Reconfiguration Modes - Altera Cyclone V Device Handbook

7-6

Reduced .mif Reconfiguration

Figure 7-1: Transceiver Channel and PLL Reconfiguration in a Transceiver Block
The following figure shows the functional blocks you dynamically reconfigure using transceiver channel
and PLL reconfiguration mode.
refclk0
refclk1
Related Information
Channel and PLL Reconfiguration" section in the Transceiver Reconfiguration Controller chapter of
the Altera Transceiver PHY IP Core User Guide
For information about transceiver channel and PLL reconfiguration.
Reduced .mif Reconfiguration
Reduce reconfiguration time by reconfiguring only the affected blocks in the transceiver channels.
This reconfiguration mode affects only the modified settings of the channel to reduce reconfiguration time
significantly. For example, in SATA/SAS applications, auto-rate negotiation must be completed within a
short period of time to meet the protocol specification. The reduced .mif method helps to reconfigure the
channel to meet these specifications. You can generate the reduced .mif files manually or by using the
xcvr_diffmifgen.exe utility.
Related Information
Altera Transceiver PHY IP Core User Guide
For information about reduced .mif creation.

Unsupported Reconfiguration Modes

The following reconfiguration modes are not supported:
Altera Corporation
clock
PLL A
mux
clock
PLL B
mux
Blocks that can be reconfigured in channel
and CMU PLL reconfiguration mode
Full Duplex Transceiver Channel
TX Channel
Logical transmitter
PLL select
Local
Divider
RX Channel
clock
RX CDR
mux
Dynamic Reconfiguration in Cyclone V Devices
CV-53007
2013.05.06
TX PMA
and
PCS
RX PMA
and
PCS
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