Embedded Memory Modes - Altera Cyclone V Device Handbook

2-10

Embedded Memory Modes

Port B
8K x 1
512 x 20 —
Embedded Memory Modes
Caution: To avoid corrupting the memory contents, do not violate the setup or hold time on any of the
memory block input registers during read or write operations. This is applicable if you use the
memory blocks in single-port RAM, simple dual-port RAM, true dual-port RAM, or ROM mode.
Table 2-9: Memory Modes Supported in the Embedded Memory Blocks
This table lists and describes the memory modes that are supported in the Cyclone V embedded memory blocks.
Memory Mode
Single-port RAM
Simple dual-port
RAM
True dual-port
RAM
Shift-register
Altera Corporation
4K x 2 2K x 4
— —
M10K MLAB
Support Support
Yes Yes You can perform only one read or one write operation at a time.
Use the read enable port to control the RAM output ports
behavior during a write operation:
Yes Yes You can simultaneously perform one read and one write
operations to different locations where the write operation
happens on port A and the read operation happens on port B.
Yes — You can perform any combination of two port operations: two
reads, two writes, or one read and one write at two different clock
frequencies.
Yes Yes You can use the memory blocks as a shift-register block to save
logic cells and routing resources.
This is useful in DSP applications that require local data storage
such as finite impulse response (FIR) filters, pseudo-random
number generators, multi-channel filtering, and auto- and cross-
correlation functions. Traditionally, the local data storage is
implemented with standard flip-flops that exhaust many logic
cells for large shift registers.
The input data width (w), the length of the taps (m), and the
number of taps (n) determine the size of a shift register
(w × m × n). You can cascade memory blocks to implement larger
shift registers.
Port A
2K x 5 1K x 8
Yes —
To retain the previous values that are held during the most
recent active read enable—create a read-enable port and
perform the write operation with the read enable port
deasserted.
To show the new data being written, the old data at that
address, or a "Don't Care" value when read-during-write occurs
at the same address location—do not create a read-enable
signal, or activate the read enable during a write operation.
Embedded Memory Blocks in Cyclone V Devices
1K x 10 512 x 16
Yes —
Description
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2013.05.06
512 x 20
Yes