Altera Cyclone V Device Handbook page 689

cv_54011
2013.12.30
The internal DMA controller initiates a data transfer only when sufficient space to accommodate the
configured burst is available in the FIFO buffer or the number of bytes to the end of transfer is less than the
configured burst-length. When the DMA master interface is configured for fixed-length bursts, it transfers
data using the most efficient combination of INCR4/8/16 and SINGLE transactions. If the DMA master
interface is not configured for fixed length bursts, it transfers data using INCR (undefined length) and
SINGLE transactions.
Host Data Buffer Alignment
The transmit and receive data buffers in system memory must be aligned to a 32-bit boundary.
Buffer Size Calculations
The driver knows the amount of data to transmit or receive. For transmitting to the card, the internal DMA
controller transfers the exact number of bytes from the FIFO buffer, indicated by the buffer size field of the
DES1 descriptor field.
If a descriptor is not marked as last (with the LD bit of the DES0 field set to 0) then the corresponding
buffer(s) of the descriptor are considered full, and the amount of valid data in a buffer is accurately indicated
by its buffer size field. If a descriptor is marked as last, the buffer might or might not be full, as indicated by
the buffer size in the DES1 field. The driver is aware of the number of locations that are valid.
is expected to ignore the remaining, invalid bytes.
Internal DMA Controller Interrupts
Interrupts can be generated as a result of various events. The idsts register contains all the bits that might
cause an interrupt. The internal DMA controller interrupt enable register (idinten) contains an enable
bit for each of the events that can cause an interrupt to occur.
There are two summary interrupts the normal interrupt summary bit (nis) and the abnormal interrupt
summary bit (ais) in the idsts register.
(ti) and receive interrupt (ri) bits in the idsts register. The ais bit is a logical OR result of the fatal bus
error interrupt (fbe), descriptor unavailable interrupt (du), and card error summary interrupt (ces) bits
in the idsts register.
Interrupts are cleared by writing a 1 to the corresponding bit position.
position, the write is ignored, and does not clear the interrupt. When all the enabled interrupts within a
group are cleared, the corresponding summary bit is set to 0. When both the summary bits are set to 0, the
interrupt signal is de-asserted.
Interrupts are not queued. If another interrupt event occurs before the driver has responded to the previous
interrupt, no additional interrupts are generated. For example, the ri bit of the idsts register indicates
that one or more data has been transferred to the host buffer.
An interrupt is generated only once for simultaneous, multiple events. The driver must scan the idsts
register for the interrupt cause.
from the BIU and internal DMA controller.
Internal DMA Controller FSM
The following steps show the internal DMA controller finite state machine (FSM) operations:
SD/MMC Controller
Send Feedback
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The nis bit results from a logical OR of the transmit interrupt
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The final interrupt signal from the controller is a logical OR of the interrupts
Host Data Buffer Alignment
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If a 0 is written to an interrupt's bit
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11-11
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The driver
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