Altera Cyclone V Device Handbook page 96

CV-52004
2014.01.10
Date
May 2013
December 2012
Clock Networks and PLLs in Cyclone V Devices
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Version
2013.05.06 Added link to the known document issues in the Knowledge Base.
Updated PCLK clock sources in hierarchical clock networks in each
spine clock per quadrant diagram.
Added PCLK networks in clock network sources section.
Updated dedicated clock input pins in clock network sources section.
Added descriptions for PLLs located in a strip.
Added information on PLL physical counters.
Updated the fractional PLL architecture diagram to add dedicated
refclk
Updated PLL support for EFB mode.
Updated the scaling factors for PLL output ports.
Updated the fractional value for PLL in fractional mode.
Moved all links to the Related Information section of respective topics
for easy reference.
Reorganized content.
2012.12.28 Added note to indicate that the figures shown are the top view of the
silicon die.
Removed DPA support.
Updated clock resources table.
Updated diagrams for GCLK, RCLK, and PCLK networks.
Updated diagram for clock sources per quadrant.
Updated dual-regional clock region for Cyclone V SoC devices support.
Restructured and updated tables for clock input pin connectivity to the
GCLK and RCLK networks.
Added tables for clock input pin connectivity to the GCLK and RCLK
networks for Cyclone V SoC devices.
Updated PCLK control block diagram.
Updated information on clock power down.
Added diagram for PLL physical counter orientation.
Updated PLL locations diagrams.
Updated fractional PLL high-level block diagram.
Removed information on
Removed information on PLL Compensation assignment in the
Quartus II software.
Updated the fractional value for PLL in fractional mode.
Reorganized content and updated template.
Changes
input port and connections.
pfdena
Document Revision History
PLL control signal.
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