Altera Cyclone V Device Handbook page 273

CV-52009
2014.01.10
Figure 9-2: User I/O BSC with IEEE Std. 1149.1 BST Circuitry for Cyclone V Devices
To Device
Circuitry
Note:
TDI
Table 9-5: Boundary-Scan Cell Descriptions for Cyclone V Devices
This table lists the capture and update register capabilities of all BSCs within Cyclone V devices.
Pin Type
User I/O pins
Dedicated
clock input
Dedicated
(24)
input
(24)
This includes the
pins.
nCE
JTAG Boundary-Scan Testing in Cyclone V Devices
Send Feedback
INJ
0
1
From or OEJ
I/O Cell
0
1
And/Or
Logic
Array
OUTJ
0
1
SDI
, , , and pins, all
TDO TMS TCK
Captures
Output OE Capture
Capture Register
Register
OUTJ OEJ
0 1
0 1
, ,
PLL_ENA VCCSEL PORSEL
Boundary-Scan Cells of a Cyclone V Device I/O Pin
Capture Update
Registers Registers
SDO
D Q D Q
INPUT INPUT
D Q D Q
OE OE
VCC
D Q D Q
OUTPUT OUTPUT
SHIFT CLOCK UPDATE HIGHZ MODE
and pin types, and
VCC GND
Input Output
Capture Update
Register Register
PIN_IN PIN_OUT
No
PIN_IN
Connect
(N.C.)
N.C.
PIN_IN
, ,
nIO_PULLUP nCONFIG
PIN_IN
0
1
0 PIN_OE
0
1
1
0 PIN_OUT
1
Output
Buffer
Global
Signals
pins do not have BSCs.
VREF
Drives
OE Update Input
Register Update
Register
PIN_OE INJ
N.C. N.C.
N.C. N.C.
, , , ,
MSEL0 MSEL1 MSEL2
9-11
Pin
Comments
—
drives
PIN_IN
to the clock
network or
logic array
drives
PIN_IN
to the control
logic
, , and
MSEL3 MSEL4
Altera Corporation