Altera Cyclone V Device Handbook page 835

cv_54016
2013.12.30
where:
[S] If S is present, the assembler sets bs to 0 and x to 1. The instruction is conditional on the state of the
request_type flag:
• request_type = Single
• The DMAC performs a DMAST instruction and it sets awlen[3:0]=0x0 so that the AXI write
transaction length is one. The DMAC ignores the v value of the dst_burst_len field in the channel control
registers.
• request_type = Burst
• The DMAC performs a DMANOP instruction. The DMAC increments the channel PC to the next
instruction. No state change occurs.
[B] If B is present, the assembler sets bs to 1 and x to 1. The instruction is conditional on the state of the
request_type flag:
• request_type = Single
• The DMAC performs a DMANOP instruction. The DMAC increments the channel PC to the next
instruction. No state change occurs.
• request_type = Burst
• The DMAC performs a DMAST.
• If you do not specify the S or B operand, the assembler sets bs to 0 and x to 0, and the DMAC always
executes a DMA store.
Note: The DMAC sets the value of the request_type flag when it executes a DMAWFP instruction.
Operation
You can only use this instruction in a DMA channel thread. If you specify the S or B operand, execution of
the instruction is conditional on the state of the request_type flag matching that of the instruction.
The DMAC only commences the burst when the MFIFO buffer contains all of the data necessary to complete
the burst transfer.
Related Information
DMAWFP
DMASTP<S | B>
Store and notify Peripheral instructs the DMAC to transfer data from the FIFO buffer to the location that
the destination address registers specifies, using AXI transactions that the DA register and channel control
registers specify. It uses the DMA channel number to access the appropriate location in the FIFO buffer.
After the DMA store is complete, and the DMAC has received a buffered write response, it issues an
acknowledgement to the peripheral that the data transfer is complete. If the dst_inc bit in the channel
control registers is set to incrementing, the DMAC updates the destination address registers after it executes
DMASTP<S|B>.
Figure 16-20: DMASTP<S|B> Instruction Encoding
Assembler syntax
DMA Controller
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on page 16-41
15
periph[4:0]
11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 1 0 bs
DMASTP<S | B>
1
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