Spi Block Diagram; Functional Description Of The Spi Controller; Protocol Details And Standards Compliance - Altera Cyclone V Device Handbook

19-2

SPI Block Diagram

SPI Block Diagram
Figure 19-1: SPI Block Diagram
SPI Master Interface
SPI Slave Interface
The functional groupings of the main interfaces to the SPI block are as follows: †
• System bus interface
• DMA peripheral request interface
• Interrupt interface
• SPI interface

Functional Description of the SPI Controller

Protocol Details and Standards Compliance

This chapter describes the functional operation of the SPI controller. †
The host processor accesses data, control, and status information about the SPI controller through the system
bus interface. The SPI also interfaces with the DMA Controller. †
Altera Corporation
SPI Master (2)
Shift Control FSM Control
Clock
TX and RX FIFO
Pre-Scale
Register Block
Slave Interface
SPI Slave (2)
Slave Interface
Register Block
Clock
TX and RX FIFO
Pre-Scale
Shift Control FSM Control
Interrupt Controller
DMA Peripheral
Request Interface
DMA Interface
DMA Interface
DMA Interface
Interrupt Controller
cv_54019
2013.12.30
MPU
IRQ IRQ
DMA
Controller
SPI Controller
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