Altera Cyclone V Device Handbook page 716

11-38
Busy Signal After CE-ATA RW_BLK Write Transfer
3. Wait until the card is not busy.
4. Check the card's transfer status. If the card is in the stand-by state, issue an SD/SDIO
SELECT/DESELECT_CARD (CMD7) command to place it in the transfer state.
Busy Signal After CE-ATA RW_BLK Write Transfer
During CE-ATA RW_BLK write transfers, the MMC busy signal might be asserted after the last block. If
the CE-ATA card device interrupt is disabled (the nIEN bit in the card device's ATA control register is set
to 1), the dto bit in the rintsts register is set to 1 even though the card sends MMC BUSY. The host
cannot issue the CMD60 command to check the ATA busy status after a CMD61 command. Instead, the
host must perform one of the following actions:
• Issue the SEND_STATUS command and check the MMC busy status before issuing a new CMD60
†
command
• Issue the CMD39 command and check the ATA busy status before issuing a new CMD60 command
For the data transfer commands, software must set the ctype register to the bus width that is programmed
†
in the card.
Data Transfer Interrupts
The controller generates an interrupt for different conditions during data transfer, which are reflected in
the following rintsts register bits:
1. dto Data transfer is over or terminated. If there is a response timeout error, the controller does not
attempt any data transfer and the Data Transfer Over bit is never set.
2. Transmit FIFO data request bit (txdr) The FIFO buffer threshold for transmitting data is reached;
software is expected to write data, if available, into the FIFO buffer.
3. Receive FIFO data request bit (rxdr) The FIFO buffer threshold for receiving data is reached; software
is expected to read data from the FIFO buffer.
4. hto The FIFO buffer is empty during transmission or is full during reception. Unless software corrects
this condition by writing data for empty condition, or reading data for full condition, the controller
cannot continue with data transfer. The clock to the card is stopped.
5. bds The card has not sent data within the timeout period.
6. dcrc A CRC error occurred during data reception.
7. sbe The start bit is not received during data reception.
8. ebe The end bit is not received during data reception, or for a write operation. A CRC error is indicated
by the card.
dcrc, sbe, and ebe indicate that the received data might have errors. If there is a response timeout, no
data transfer occurs.
Single-Block or Multiple-Block Read
To implement a single-block or multiple-block read, the software performs the following steps:
1. Write the data size in bytes to the bytcnt register. For a multi-block read, bytcnt must be a multiple
of the block size.
2. Write the block size in bytes to the blksiz register. The controller expects data to return from the card
in blocks of size blksiz.
3. If the read round trip delay, including the card delay, is greater than half of sdmmc_clk_divided,
write to the card threshold control register (cardthrctl) to ensure that the card clock does not stop
in the middle of a block of data being transferred from the card to the host. For more information, refer
to Card Read Threshold.
Altera Corporation
†
†
†
†
†
†
†
†
†
†
†
†
†
†
†
†
†
SD/MMC Controller
Send Feedback
cv_54011
2013.12.30
†