Watchdog Timer Programming Model; Setting The Timeout Period Values; Selecting The Output Response Mode; Enabling And Initially Starting A Watchdog Timer - Altera Cyclone V Device Handbook

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Watchdog Timer Programming Model

Watchdog Timer Programming Model

Setting the Timeout Period Values

The watchdog timers have a dual timeout period. The counter uses the initial start timeout period value the
first the timer is started. All subsequent restarts use the restart timeout period. The valid values are 2
clock cycles, where i is an integer from 0 to 15. To set the programmable timeout periods, perform the
following steps:
Before you begin
Set the timeout values before enabling the timer.
1. To set the initial start timeout period, write i to the timeout period for initialization field (top_init)
of the watchdog timeout range register (wdt_torr).
2. To set the restart timeout period, write i to the timeout period field (top) of the wdt_torr register.

Selecting the Output Response Mode

The watchdog timers have two output response modes (as described in Watchdog Timer Counter). To select
the desired mode, perform one of the following steps:
1. To generate a system reset request when a timeout occurs, write 0 to the output response mode bit (rmod)
of the watchdog timer control register (wdt_cr).
2. To generate an interrupt and restart the timer when a timeout occurs, write 1 to the rmod field of the
wdt_cr register.
If a restart occurs at the same time the watchdog counter reaches zero, a system reset is not generated. †
Related Information
Watchdog Timer Counter

Enabling and Initially Starting a Watchdog Timer

1. To enable and start a watchdog timer, write the value 1 to the watchdog timer enable bit (wdt_en) of
the wdt_cr register.

Reloading a Watchdog Counter

1. To reload a watchdog counter, write the value 0x76 to the counter restart register (wdt_crr). This
unique 8-bit value is used as a safety feature to prevent accidental restarts.

Pausing a Watchdog Timer

Pausing the watchdog timers is controlled by the L4 watchdog debug register (wddbg) in the system manager.
Related Information
Features of the System Manager
For more information, refer to the System Manager chapter of the Cyclone V Device Handbook, Volume 3.

Disabling and Stopping a Watchdog Timer

The watchdog timers are disabled and stopped only by resetting them from the reset manager.
Altera Corporation
on page 24-2
on page 14-1
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Watchdog Timer
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