Watchdog Timer Pause Mode; Watchdog Timer Clocks; Watchdog Timer Resets - Altera Cyclone V Device Handbook

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2013.12.30
MPU subsystem. If the interrupt is not serviced by software before a second timeout occurs, the timer
generates a reset request.
If a restart occurs at the same time the watchdog counter reaches zero, an interrupt is not generated.
Related Information
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Watchdog Timer Clocks

• Setting the Timeout Period Values
• Selecting the Output Response Mode
• Reloading a Watchdog Counter

Watchdog Timer Pause Mode

The watchdog timers can be paused during debugging. Pausing the watchdog timers is controlled by the
system manager. The following options are available:
• Pause the timer while either CPU0 or CPU1 is in debug mode
• Pause the timer while only CPU1 is in debug mode
• Pause the timer while only CPU0 is in debug mode
• Do not pause the timer
When pause mode is enabled, the system manager pauses the watchdog timer while debugging. When pause
mode is disabled, the watchdog timer runs even while debugging.
When the system manager exits reset, the watchdog pausing feature is enabled for both CPUs by default.
Related Information
Pausing a Watchdog Timer
Watchdog Timer Clocks
Each watchdog timer is connected to the osc1_clk clock so that timer operation is not dependent on the
phase-locked loops (PLLs) in the clock manager. This independence allows recovery from software that
inadvertently programs the PLLs in the clock manager incorrectly.
Related Information
Clock Manager
For more information, refer to the Clock Manager chapter.

Watchdog Timer Resets

Watchdog timers are reset by a cold or warm reset from the reset manager, and are disabled when exiting
reset. †
Related Information
Reset Manager
For more information, refer to the Reset Manager chapter.
Watchdog Timer
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Watchdog Timer Pause Mode
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