Altera Cyclone V Device Handbook page 90

CV-52004
2014.01.10
Figure 4-33: Automatic Clock Switchover Circuit Block Diagram
This figure shows a block diagram of the automatic switchover circuit built into the PLL.
When the current reference clock is not present, the clock sense block automatically switches to the backup
clock for PLL reference. You can select a clock source as the backup clock by connecting it to the
port of the PLL in your design.
The clock switchover circuit sends out three status signals—
the PLL to implement a custom switchover circuit in the logic array.
In automatic switchover mode, the
inputs. When they are asserted, the clock sense block detects that the corresponding clock input has stopped
toggling. These two signals are not valid if the frequency difference between
than 20%.
The
activeclock
reference clock to the PLL. When the frequency difference between the two clock inputs is more than 20%,
the
activeclock
Note: Glitches in the input clock may cause the frequency difference between the input clocks to be more
than 20%.
Use the switchover circuitry to automatically switch between
clock to the PLL stops toggling. You can switch back and forth between
times when one of the two clocks fails and the other clock is available.
For example, in applications that require a redundant clock with the same frequency as the reference clock,
the switchover state machine generates a signal (
case,
inclk1
When using automatic clock switchover mode, the following requirements must be satisfied:
Both clock inputs must be running when the FPGA is configured.
The period of the two clock inputs can differ by no more than 20%.
If the current clock input stops toggling while the other clock is also not toggling, switchover is not initiated
and the
clkbad[0..1]
Clock Networks and PLLs in Cyclone V Devices
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inclk0
inclk1
Multiplexer
Out
clkbad[0]
signal indicates which of the two clock inputs (
signal is the only valid status signal.
becomes the reference clock for the PLL.
signals are not valid. If both clock inputs are not the same frequency, but their period
Clock
Switchover
Sense
State Machine
clksw
Clock Switch
Control Logic
N Counter
refclk
clkbad[0]
and signals indicate the status of the two clock
clkbad[1]
inclk0
inclk0
) that controls the multiplexer select input. In this
clksw
Automatic Switchover
clkbad[0]
clkbad[1]
activeclock
clkswitch
PFD
fbclk
, , and
clkbad[1] activeclock
and
inclk0 inclk1
or ) is being selected as the
inclk1
and when the current reference
inclk1
and any number of
inclk0 inclk1
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4-33
inclk1
—from
is greater