Altera Cyclone V Device Handbook page 78

CV-52004
2014.01.10
Figure 4-21: PLL Locations for Cyclone V SE A2 and A4 Devices, and Cyclone V SX C2 and C4 Devices
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
Figure 4-22: PLL Locations for Cyclone V SE A5 and A6 Devices, Cyclone V SX C5 and C6 Devices, and
Cyclone V ST D5 and D6 Devices
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
Clock Networks and PLLs in Cyclone V Devices
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CLK[6,7][p,n]
2
FRACTIONALPLL_X0_Y54
PLL Strip
2
FRACTIONALPLL_X0_Y30
2
FRACTIONALPLL_X0_Y14
4
FRACTIONALPLL_X0_Y1
CLK[0..3][p,n]
CLK[6,7][p,n]
2
FRACTIONALPLL_X0_Y74
PLL Strip
2
FRACTIONALPLL_X0_Y56
2
FRACTIONALPLL_X0_Y32
2
4
FRACTIONALPLL_X0_Y15
4
FRACTIONALPLL_X0_Y1
CLK[0..3][p,n]
PLL Locations in Cyclone V Devices
Pins
2 Logical Clocks
FRACTIONALPLL_X68_Y1
4 Logical Clocks
CLK[2,3]
Pins
Pins
2 Logical Clocks
FRACTIONALPLL_X89_Y1
4 Logical Clocks
CLK[2,3]
Pins
2
Logical Clocks
4
2
Pins
Logical
CLK[4,5][p,n]
Clocks
2 Logical
Clocks
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