Altera Cyclone V Device Handbook page 487

cv_54002
2013.12.30
The counter outputs from the SDRAM PLL can be gated off directly under software control. The divider
values for each clock are set by registers in the clock manager.
Table 2-6: SDRAM PLL Output Assignments
PLL
SDRAM
The following figure shows clock gating for SDRAM PLL clock group. Clock gate blocks in the diagram
indicate clocks which may be gated off under software control. Software is expected to gate these clocks off
prior to changing any PLL or divider settings that might create incorrect behavior on these clocks.
Figure 2-5: SDRAM Clock Group Divide and Gating
The SDRAM PLL output clocks can be phase shifted in real time in increments of 1/8 the VCO frequency.
Maximum number of phase shift increments is 4096.
Clock Manager
Send Feedback
Output Counter
C0
C1
C2
C5
Note: The maximum frequency depends on the speed grade of the
device.
ddr_dqs_base_clk
SDRAM
C0
PLL
ddr_2x_dqs_base_clk
C1
ddr_dq_base_clk
C2
Unused
C3
C4 Unused
h2f_user2_base_clk
C5
Clock Name
Up to varies (1)
ddr_dqs_base_
clk
Up to ddr_dqs_
ddr_2x_dqs_
base_clk x 2
base_clk
Up to ddr_dqs_
ddr_dq_base_
base_clk
clk
osc1_clk to varies
h2f_user2_
(1)
base_clk
Clock Gate
Clock Gate
Clock Gate
Clock Gate
SDRAM Clock Group
Frequency Phase Shift Control
Yes
Yes
Yes
Yes
ddr_dqs_clk
ddr_2x_dqs_clk
ddr_dq_clk
h2f_user2_clock
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