Altera Cyclone V Device Handbook page 349

CV-53002
2013.05.06
Figure 2-9: Three Non-Bonded Transmitter Channels Driven by CMU PLL using x1 Clock Line Within a
Transceiver Bank
Transceiver Clocking in Cyclone V Devices
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x1_top
TX PMA Ch5
TX PMA Ch4
TX PMA Ch3
Channels 0, 1, 2
Both Parallel and Serial Clocks
Serial Clock
Parallel Clock
Non-Bonded Channel Configurations
TX PCS Ch5
Local Clock Divider
Clock Divider
TX PCS Ch4
Central Clock Divider
Clock Divider
TX PCS Ch3
Local Clock Divider
Clock Divider
Data Path
Unused Resources
2-11
CMU PLL
CMU PLL
CMU PLL
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