Altera Cyclone V Device Handbook page 808

16-12
DMAC Length Management
When the DMAC executes a DMAWFP peripheral instruction, it halts execution of the thread and waits for
the peripheral to send a request. When the peripheral sends the request, the DMAC sets the request flags
depending on the state of the following signals:
• drtype_<x>[1:0]
• drtype_<x>[1:0]=b00 request_type <x> = Single
• drtype_<x>[1:0]=b01 request_type <x> = Burst
• drlast_<x> The DMAC sets the state of the request_last flag:
• drlast_<x>=0 request_last <x> = 0
• drlast_<x>=1 request_last <x> = 1
Note:
If the DMAC executes a DMAWFP single or DMAWFP burst instruction then the DMAC sets:
• The request_type<x> flag to Single or Burst, respectively
• The request_last<x> flag to 0
DMALPFE is an assembler directive which forces the associated DMALPEND instruction to have its nf bit
set to 0. This creates a program loop that does not use a loop counter to terminate the loop.
The DMAC exits the loop when the request_last flag is set to 1.
The DMAC conditionally executes the following instructions, depending on the state of the request_type
and request_last flags:
• DMALD , DMAST , DMALPEND
When these instructions use the optional B|S suffix then the DMAC executes a DMANOP if the
request_type flag does not match.
• DMALDP<B|S> , DMASTP<B|S>
The DMAC executes a DMANOP if the request_type <x> flag does not match the B|S
• DMALPEND
When the nf bit is 0, the DMAC executes a DMANOP if the request_last flag is set.
Use the DMALDB, DMALDPB, DMASTB and DMASTPB instructions if you require the DMAC to issue a burst
transfer when the DMAC receives a burst request. The values in the CCR n register control the amount of
data that the DMAC transfers.
Use the DMALDS, DMALDPS, DMASTS and DMASTPS instructions if you require the DMAC to issue a single
transfer when the DMAC receives a single request. The DMAC ignores the value of the src_burst_len and
dst_burst_len fields in the CCRn register and sets the arlen[3:0] or awlen[3:0] buses to 0x0.
DMAC Length Management
The DMAC controls the total amount of data. The peripheral uses the peripheral request interface to notify
the DMAC when it requires the DMAC to transfer data to or from the peripheral. The DMA channel thread
controls how the DMAC responds to the peripheral requests.
Altera Corporation
The DMAC sets the state of the request_type flag:
cv_54016
2013.12.30
DMA Controller
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