Altera Cyclone V Device Handbook page 756

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the last word of an indirect transfer. On the final read, the external master may issue a 32-bit, 16-bit or 8-bit
read to complete the transfer. If there are less than four bytes of data to read on the last transfer, the external
master can still issue a 32-bit read and the quad SPI controller will pad the upper bits of the response data
with zeros.
Assuming the requested data is present in the SRAM at the time the data slave read is received by the quad
SPI controller, the data is fetched from SRAM and the response to the read burst is achieved with minimum
latency. If the requested data is not immediately present in the SRAM, the data slave interface enters a wait
state until the data has been read from flash memory into SRAM. Once the data has been read from SRAM
by the external master, the quad SPI controller frees up the associated resource in the SRAM. If the SRAM
is full, reads on the SPI interface are backpressured until space is available in the SRAM. The quad SPI
controller completes any current read burst, waits for SRAM to free up, and issues a new read burst at the
address where the previous burst was terminated.
The processor can also use the SRAM fill level in the SRAM fill register (sramfill) to control when data
should be fetched from the SRAM.
Another alternative is to use the fill level watermark of the SRAM, which you configure in the indrdwater
register. When the SRAM fill level passes the watermark level, the indirect transfer watermark interrupt is
generated. You can disable the watermark feature by writing zero to the indrdwater register.
For the final bytes of data read by the quad SPI controller and placed in the SRAM, if the watermark level
is greater than zero, the indirect transfer watermark interrupt is generated even when the actual SRAM fill
level has not risen above the watermark.
If the address of the read access is outside the range of the indirect trigger address, one of the following
actions occurs:
• When direct access mode is enabled, the read uses direct access mode.
• When direct access mode is disabled, the slave returns an error back to the requesting master.
You can cancel an indirect operation by setting the cancel indirect read bit (cancel) of the indrd register
to 1. For more information, refer to the Indirect Read Operation with DMA Disabled" section.
Related Information
Indirect Read Operation with DMA Disabled
Indirect Write Operation
An indirect write operation programs data from the SRAM to the flash memory. The indirect write operations
are controlled by the following registers:
• Indirect write transfer register (indwr)
• Indirect write transfer watermark register (indwrwater)
• Indirect write transfer start address register (indwrstaddr)
• Indirect write transfer number bytes register (indwrcnt)
• indaddrtrig register
These registers need to be configured prior to issuing indirect write operations. The start address needs to
be defined in the indwrstaddr register and the total number of bytes to be written is specified in the
indwrcnt register. The start indirect write bit (start) of the indwr register triggers the indirect write
operation from the SRAM to the flash memory.
To write data from the SRAM to the flash device, an external master issues 32-bit write transactions to the
data slave. The address of the write access must be in the indirect address range. You can configure the
indirect address through the indaddrtrig register. The external master can issue 32-bit writes until the
last word of an indirect transfer. On the final write, the external master may issue a 32-bit, 16-bit or 8-bit
Quad SPI Flash Controller
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Indirect Write Operation
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