Altera Cyclone V Device Handbook page 809

cv_54016
2013.12.30
The following constraints apply to DMAC length management:
• The total quantity of data for all the single requests from a peripheral must be less than the quantity of
data for a burst request for that peripheral.
Note:
• After the peripheral sends a burst request, the peripheral must not send a single request until the DMAC
acknowledges that the burst request is complete.
Program the DMAWFP single instruction when you require the program thread to halt execution until the
peripheral request interface receives any request type.
• Single
from the FIFO buffer and continues program execution.
• Burst If the head entry in the request FIFO buffer is a burst request type, the DMAC leaves the entry
in the FIFO buffer and continues program execution.
Note:
Program the DMAWFP burst instruction when you require the program thread to halt execution until the
peripheral request interface receives a burst request.
• Single If the head entry in the request FIFO buffer is a single request type, the DMAC removes the entry
from the FIFO buffer and continues program execution.
• Burst If the head entry in the request FIFO buffer is a burst request type, the DMAC pops the entry
from the FIFO buffer and continues program execution.
Program the DMALDP instruction when you require the DMAC to send an acknowledgement to the peripheral
when it completes the AXI read transfers. Similarly, use the DMASTP instruction when you require the
DMAC to send an acknowledgement to the peripheral when it completes the AXI write transfers. The DMAC
uses the acknowledge bus to signal a transfer acknowledgement to peripheral <x>.
Note: The DMAC sends an acknowledgement for a read transaction when the rvalid and rlast signals
are high and for a write transaction when bvalid signal is high. The DMAC might send an
acknowledgement to the peripheral while the transfer of write data to the end destination is still in
progress.
Use the DMAFLUSHP instruction to reset the request FIFO buffer for the peripheral request interface. After
the DMAC executes DMAFLUSHP, it ignores peripheral requests until the peripheral acknowledges the flush
request. This enables the DMAC and peripheral to synchronize with each other.
ARM Protocol
The DMA peripheral request interface communicates with peripherals by either the ARM protocol or the
Synopsys protocol.
For peripherals using the ARM protocol, clock-crossing logic is the only logic between the DMA and the
peripheral.
DMA Controller
Send Feedback
The CCRn register controls how much data is transferred for a burst request and a single request.
Altera recommends that you do not update a CCRn register when a transfer is in progress for
channel n.
If the head entry in the request FIFO buffer is a single request type, the DMAC pops the entry
The burst request entry remains in the request FIFO buffer until the DMAC executes a DMAWFP
burst instruction or a DMAFLUSHP instruction.
16-13
ARM Protocol
Altera Corporation