Clock Data Recovery Manual Lock Mode Reset Sequence; Control Settings For Cdr Manual Lock Mode - Altera Cyclone V Device Handbook

3-12

Clock Data Recovery Manual Lock Mode Reset Sequence

Register Name
reset_tx_digital
reset_rx_analog
reset_rx_digital
reset_ch_bitmask
pll_powerdown
Related Information
Altera Transceiver PHY IP Core User Guide
For information about register addresses.
Clock Data Recovery Manual Lock Mode Reset Sequence
Use the clock data recovery (CDR) manual lock mode to override the default CDR automatic lock mode.
The two control signals to enable and control the CDR in manual lock mode are rx_set_locktoref
and rx_set_locktodata.

Control Settings for CDR Manual Lock Mode

Use the following control signals to reset the transceiver when the CDR is in manual lock mode.
Table 3-5: Control Settings for the CDR in Manual Lock Mode
rx_set_locktoref
0
1
X
Altera Corporation
When you set this register to high, the tx_digitalreset
signal is asserted in every channel that is enabled for reset control
through the reset_ch_bitmask register. To deassert the
tx_digitalreset signal, set the reset_tx_digital
register to 0.
When you set this register to high, the rx_analogreset
signal is asserted in every channel that is enabled for reset control
through the reset_ch_bitmask register. To deassert the
rx_analogreset signal, set the reset_rx_analog
register to 0.
When you set this register to high, the rx_digitalreset
signal is asserted in every channel that is enabled for reset control
through the reset_ch_bitmask register. To deassert the
rx_digitalreset signal, set the reset_rx_digital
register to 0.
The registers provide an option to enable or disable certain
channels in a PHY IP instance for reset control. By default, all
channels in a PHY IP instance are enabled for reset control.
When asserted, the TX phase-locked loop (PLL) is turned off.
rx_set_locktodata
0
0
1
Description
CDR Lock Mode
Automatic
Manual-RX CDR LTR
Manual-RX CDR LTD
Transceiver Reset Control in Cyclone V Devices
CV-53003
2013.05.06
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