Scan Manager; Features Of The Scan Manager - Altera Cyclone V Device Handbook

2013.12.30
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The scan manager is used to configure and manage the HPS I/O pins, and communicate with the FPGA
JTAG test access port (TAP) controller. The scan manager drives the HPS I/O scan chains to configure the
I/O bank properties before the pins are used by the peripherals in HPS. The scan manager can also optionally
communicate with the FPGA JTAG TAP controller to send commands for purposes such as managing cyclic
redundancy check (CRC) errors detected by the FPGA control block. When the scan manager communicates
with the FPGA JTAG TAP controller, input on the FPGA JTAG pins is ignored.
The scan manager contains an ARM
scan-chain JTAG master interface. One scan chain connects to the FPGA JTAG and uses the standard JTAG
signals. Four other scan chains connect to the HPS I/O banks, using the JTAG clock and data outputs as a
parallel-to-serial converter.
Related Information
Info center
For more information about the ARM JTAG-AP, refer to the ARM Debug Interface v5 Architecture
Specification, which you can download from the ARM info center website.

Features of the Scan Manager

• Drives all the I/O scan chains for HPS I/O banks
• Allows the HPS to access the FPGA JTAG TAP controller
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JTAG Access Port (JTAG-AP). The JTAG-AP implements a multiple

Scan Manager

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