Altera Cyclone V Device Handbook page 936

cv_54019
2013.12.30
There are four possible transfer modes on the SPI controller for performing SPI serial transactions; refer to
"Transfer Modes" . For transmit and receive transfers (transfer mode field (9:8) of the Control Register 0 =
0), data transmitted from the SPI controller to the external serial device is written into the transmit FIFO
buffer. Data received from the external serial device into the SPI controller is pushed into the receive FIFO
buffer. †
Note: For transmit only transfers (transfer mode field (9:8) of the Control Register 0 = 1), data transmitted
from the SPI controller to the external serial device is written into the transmit FIFO buffer. As the
data received from the external serial device is deemed invalid, it is not stored in the SPI receive FIFO
buffer. †
For receive only transfers (transfer mode field (9:8) of the Control Register 0 = 2), data transmitted from the
SPI controller to the external serial device is invalid, so a single dummy word is written into the transmit
FIFO buffer to begin the serial transfer. The txd output from the SPI controller is held at a constant logic
level for the duration of the serial transfer. Data received from the external serial device into the SPI controller
is pushed into the receive FIFO buffer. †
For eeprom_read transfers (transfer mode field [9:8] of the Control Register 0 = 3), opcode and/or EEPROM
address are written into the transmit FIFO buffer. During transmission of these control frames, received
data is not captured by the SPI master. After the control frames have been transmitted, receive data from
the EEPROM is stored in the receive FIFO buffer.
Related Information
Transfer Modes
Texas Instruments Synchronous Serial Protocol (SSP)
Data transfers begin by asserting the frame indicator line (ss_0_n) for one serial clock period. Data to be
transmitted are driven onto the txd line one serial clock cycle later; similarly data from the slave are driven
onto the rxd line. Data are propagated on the rising edge of the serial clock (sclk_out/sclk_in) and
captured on the falling edge. The length of the data frame ranges from 4 to 16 bits.
Note: The slave select signal (ss_0_n) takes effect only when used as slave SPI. For master SPI, the data
transmission begins as soon as the output enable signal is deasserted.
Figure 19-7: SSP Serial Format
ss_0_n/ss_in_n
Continuous data frames are transferred in the same way as single data frames. The frame indicator is asserted
for one clock period during the same cycle as the LSB from the current transfer, indicating that another data
frame follows. †
SPI Controller
Send Feedback
on page 19-6
sclk_out/in
txd/rxd
ss_oe_n
Texas Instruments Synchronous Serial Protocol (SSP)
MSB LSB
Altera Corporation
19-13