Altera Cyclone V Device Handbook page 447

TOC-8
Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual
SD/MMC Controller Address Map and Register Definitions...........................................................11-72
Document Revision History...................................................................................................................11-72
Quad SPI Flash Controller................................................................................12-1
Features of the Quad SPI Flash Controller.............................................................................................12-1
Quad SPI Flash Controller Block Diagram and System Integration..................................................12-2
Functional Description of the Quad SPI Flash Controller...................................................................12-3
Overview.........................................................................................................................................12-3
Data Slave Interface.......................................................................................................................12-3
Register Slave Interface.................................................................................................................12-3
Direct Access Mode.......................................................................................................................12-3
Indirect Access Mode....................................................................................................................12-4
Local Memory Buffer.....................................................................................................................12-6
DMA Peripheral Request Controller..........................................................................................12-7
STIG Operation..............................................................................................................................12-8
SPI Legacy Mode............................................................................................................................12-8
Configuring the Flash Device.......................................................................................................12-9
XIP Mode......................................................................................................................................12-10
Write Protection..........................................................................................................................12-11
Data Slave Sequential Access Detection...................................................................................12-11
Clocks............................................................................................................................................12-11
Resets.............................................................................................................................................12-11
Interrupts......................................................................................................................................12-12
Interface Signals...........................................................................................................................12-13
Quad SPI Flash Controller Programming Model...............................................................................12-14
Setting Up the Quad SPI Flash Controller...............................................................................12-14
Indirect Read Operation with DMA Disabled.........................................................................12-14
Indirect Read Operation with DMA Enabled..........................................................................12-15
Indirect Write Operation with DMA Disabled.......................................................................12-15
Indirect Write Operation with DMA Enabled........................................................................12-16
XIP Mode Operations.................................................................................................................12-16
Quad SPI Flash Controller Address Map and Register Definitions.................................................12-18
Document Revision History...................................................................................................................12-18
FPGA Manager..................................................................................................13-1
Features of the FPGA Manager................................................................................................................13-1
FPGA Manager Block Diagram and System Integration.....................................................................13-2
Functional Description of the FPGA Manager......................................................................................13-3
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