Altera Cyclone V Device Handbook page 567

cv_54006
2013.12.30
Functional Description
The global timer is accessible by the processors using memory-mapped access through the SCU. The global
timer has the following features:
• 64-bit incrementing counter with an auto-incrementing feature. It continues incrementing after sending
interrupts.
• Memory-mapped in the private memory region.
• Accessed at reset in Secure State only. It can only be set once, but secure code can read it at any time.
• Accessible to both Cortex-A9 processors in the MPCore.
Implementation Details
Each Cortex-A9 processor has a private 64-bit comparator that generates a private interrupt when the counter
reaches the specified value. Each Cortex-A9 processor uses the banked ID, ID27, for this interrupt. ID27 is
sent to the GIC as a Private Peripheral Interrupt (PPI).
The global timer are clocked by mpu_periph_clk, running at ¼ the rate of mpu_clk.
For more information about the global timer, refer to "About the Global Timer" in the Global timer, Private
timers, and Watchdog registers chapter of the Cortex-A9 MPCore Technical Reference Manual, available on
the ARM website (infocenter.arm.com).
Related Information
ARM Infocenter (www.infocenter.arm.com)
Snoop Control Unit
The SCU manages data traffic for the Cortex-A9 processors and the memory system, including the L2 cache.
In a multi-master system, the processors and other masters can operate on shared data. The SCU ensures
that each processor operates on the most up-to-date copy of data, maintaining cache coherency.
Functional Description
The SCU is used to connect the Cortex-A9 processors and the ACP to the L2 cache controller. The SCU
performs the following functions:
• When the processors are set to SMP mode, the SCU maintains data cache coherency between the
processors.
Note:
• Initiates L2 cache memory accesses
• Arbitrates between processors requesting L2 access
• Manages ACP access with cache coherency capabilities.
For more information about the SCU, refer to the Snoop Control Unit chapter of the Cortex-A9 MPCore
Technical Reference Manual, available on the ARM website (infocenter.arm.com).
Related Information
ARM Infocenter (www.infocenter.arm.com)
Cortex-A9 Microprocessor Unit Subsystem
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The SCU does not maintain coherency of the instruction caches.
Functional Description
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