Altera Cyclone V Device Handbook page 622

8-22
AXI Port
Name
Write Response Channel Signals
BID
BRESP
BVALID
BREADY
Read Address Channel Signals
ARID
ARADDR
ARLEN
ARSIZE
ARBURST
ARREADY
ARVALID
Altera Corporation
Bits Direction
4 Out
2 Out
1 Out
1 In
4 In
32 In
4 In
3 In
2 In
1 Out
1 In
Function
Write response transfer ID
Write response status
Write response valid signal
Write response ready signal
Read identification tag
Read address
Read burst length
Width of the transfer size
Burst type
Indicates ready for a read command
Indicates valid read command
SDRAM Controller Subsystem
cv_54008
2013.12.30
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