Resets; Interrupts; Timer Programming Model; Initialization - Altera Cyclone V Device Handbook

cv_54023
2013.12.30
SP timer 0 and SP timer 1 must be disabled before l4_sp_clk is changed to another frequency. You can
then re-enable the timer once the clock frequency change takes effect. You cannot change the frequency of
OSC1 timer 0 and OSC1 timer 1.
Related Information
Clock Manager
For more information about clock performance, refer to the Clock Manager chapter.

Resets

The timers are reset by a cold or warm reset. Resetting the timers produces the following results in the
following order:
1. The timer is disabled.
2. The interrupt is enabled.
3. The timer enters free-running mode.
4. The timer count load register value is set to zero.

Interrupts

The timer1 interrupt status (timer1intstat) and timer1 end of interrupt (timer1eoi) registers handle
the interrupts. The timer1intstat register allows you to read the status of the interrupt. Reading from
the timer1eoi register returns the value 0 and clears the interrupt. †
The timer1 control register (timer1controlreg) contains the timer1 interrupt mask bit
(timer1_interrupt_mask)to mask the interrupt. In both the free-running and user-defined count
modes of operation, the timer generates an interrupt signal when the timer count reaches zero and the
interrupt mask bit of the control register is high.
If the timer interrupt is set, then it is cleared when the timer is disabled.

Timer Programming Model

Initialization

To initialize the timer, perform the following steps: †
1. Initialize the timer through the timer1controlreg register: †
• Disable the timer by writing a 0 to the timer1 enable bit (timer1_enable) of the
timer1controlreg register. †
Note:
• Program the timer mode user-defined count or free-running by writing a 0 or 1, respectively, to
the timer1 mode bit (timer1_mode) of the timer1controlreg register. †
• Set the interrupt mask as either masked or not masked by writing a 1 or 0, respectively, to the
timer1_interrupt_mask bit of the timer1controlreg register. †
2. Load the timer counter value into the timer1loadcount register. †
Timer Introduction
Send Feedback
on page 2-1
Before writing to a timer1 load count register (timer1loadcount), you must disable the timer
by writing a 0 to the timer1_enable bit of the timer1controlreg register to avoid
potential synchronization problems. †
23-3
Resets
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