Altera Cyclone V Device Handbook page 578

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L2 Cache Event Monitoring

For more information about the built-in L2 event monitoring capability, refer to "Implementation details"

in the Functional Overview chapter of the CoreLink Level 2 Cache Controller L2C-310 Technical Reference

Manual, available on the ARM website (infocenter.arm.com).

In addition, the L2 cache events can be captured and timestamped using dedicated debugging circuitry.

For more information about L2 event capture, refer to the Debug chapter of the Cortex-A9 MPCore Technical

Reference Manual, available on the ARM website (infocenter.arm.com).

Related Information

ARM Infocenter (www.infocenter.arm.com)

Altera Corporation

Data read lookup to the L2 cache. Subsequently results

in a hit or miss.

Data write hit in the L2 cache.

Data write lookup to the L2 cache. Subsequently

results in a hit or miss.

Data write lookup to the L2 cache with write-through

attribute. Subsequently results in a hit or miss.

Prefetch hint allocated into the L2 cache.

Prefetch hint hits in the L2 cache.

Prefetch hint received by slave port S0.

Prefetch hint received by slave port S1.

Allocation of a prefetch generated by L2 cache

controller into the L2 cache.

Instruction read hit in the L2 cache.

Instruction read lookup to the L2 cache. Subsequently

results in a hit or miss.

Secure privileged non-invasive debug enable.

Speculative read confirmed in slave port S0.

Speculative read confirmed in slave port S1.

Speculative read received by slave port S0.

Speculative read received by slave port S1.

Allocation into the L2 cache caused by a write, with

write-allocate attribute, miss.

Cortex-A9 Microprocessor Unit Subsystem

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