Altera Cyclone V Device Handbook page 455

TOC-16
Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual
HPS Component Interfaces...............................................................................28-1
Memory-Mapped Interfaces.....................................................................................................................28-2
Clocks..........................................................................................................................................................28-5
Resets...........................................................................................................................................................28-6
Debug and Trace Interfaces......................................................................................................................28-6
Peripheral Signal Interfaces......................................................................................................................28-7
Other Interfaces..........................................................................................................................................28-7
Document Revision History.....................................................................................................................28-9
HPS Simulation Support...................................................................................29-1
Clock and Reset Interfaces........................................................................................................................29-2
FPGA-to-HPS AXI Slave Interface..........................................................................................................29-4
HPS-to-FPGA AXI Master Interface......................................................................................................29-4
Lightweight HPS-to-FPGA AXI Master Interface................................................................................29-5
FPGA-to-HPS SDRAM Interface............................................................................................................29-5
HPS-to-FPGA MPU General Purpose I/O Interface............................................................................29-5
HPS-to-FPGA MPU Event Interface......................................................................................................29-6
FPGA-to-HPS Interrupts Interface.........................................................................................................29-6
HPS-to-FPGA Debug APB Interface......................................................................................................29-7
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FPGA-to-HPS Bridge....................................................................................................................28-2
HPStoFPGA and Lightweight HPS-to-FPGA Bridges.............................................................28-3
FPGA-to-HPS SDRAM Interface................................................................................................28-3
Alternative Clock Inputs to HPS PLLs........................................................................................28-5
User Clocks.....................................................................................................................................28-5
AXI Bridge FPGA Interface Clocks.............................................................................................28-5
SDRAM Clocks..............................................................................................................................28-5
HPS-to-FPGA Reset Interfaces....................................................................................................28-6
HPS External Reset Sources..........................................................................................................28-6
Trace Port Interface Unit..............................................................................................................28-6
FPGA System Trace Macrocell Events Interface.......................................................................28-6
FPGA Cross Trigger Interface......................................................................................................28-6
Debug APB Interface.....................................................................................................................28-7
MPU Standby and Event Interfaces............................................................................................28-8
FPGA-to-HPS Interrupts..............................................................................................................28-8
General-Purpose Interfaces..........................................................................................................28-8
Clock Interface...............................................................................................................................29-2
Reset Interface................................................................................................................................29-3