Altera Cyclone V Device Handbook page 5

Guideline: Ensure Compatible V
Guideline: Pin Restrictions.................................................................................................5-18
VREF
Guideline: Observe Device Absolute Maximum Rating for 3.3 V Interfacing......................5-18
Guideline: Adhere to the LVDS I/O Restrictions and Differential Pad Placement
Rules...........................................................................................................................................5-19
I/O Banks Locations in Cyclone V Devices............................................................................................5-19
I/O Banks Groups in Cyclone V Devices...............................................................................................5-21
Modular I/O Banks for Cyclone V E Devices............................................................................5-22
Modular I/O Banks for Cyclone V GX Devices.........................................................................5-23
Modular I/O Banks for Cyclone V GT Devices.........................................................................5-24
Modular I/O Banks for Cyclone V SE Devices..........................................................................5-25
Modular I/O Banks for Cyclone V SX Devices..........................................................................5-26
Modular I/O Banks for Cyclone V ST Devices..........................................................................5-27
I/O Element Structure in Cyclone V Devices........................................................................................5-27
I/O Buffer and Registers in Cyclone V Devices.........................................................................5-27
Programmable IOE Features in Cyclone V Devices.............................................................................5-29
Programmable Current Strength.................................................................................................5-30
Programmable Output Slew-Rate Control.................................................................................5-31
Programmable IOE Delay.............................................................................................................5-31
Programmable Output Buffer Delay...........................................................................................5-31
Programmable Pre-Emphasis......................................................................................................5-32
Programmable Differential Output Voltage..............................................................................5-32
I/O Pins Features for Cyclone V Devices...............................................................................................5-33
Open-Drain Output.......................................................................................................................5-33
Bus-Hold Circuitry........................................................................................................................5-33
Pull-up Resistor..............................................................................................................................5-34
On-Chip I/O Termination in Cyclone V Devices.................................................................................5-34
R OCT without Calibration in Cyclone V Devices..................................................................5-35
S
R OCT with Calibration in Cyclone V Devices........................................................................5-36
S
R OCT with Calibration in Cyclone V Devices.......................................................................5-38
T
Dynamic OCT in Cyclone V Devices..........................................................................................5-40
LVDS Input R OCT in Cyclone V Devices..............................................................................5-41
D
OCT Calibration Block in Cyclone V Devices...........................................................................5-42
External I/O Termination for Cyclone V Devices.................................................................................5-44
Single-ended I/O Termination.....................................................................................................5-45
Differential I/O Termination.......................................................................................................5-47
Dedicated High-Speed Circuitries...........................................................................................................5-52
High-Speed Differential I/O Locations.......................................................................................5-52
LVDS SERDES Circuitry..............................................................................................................5-54
Cyclone V Device Handbook Volume 1: Device Interfaces and Integration
and V
CCIO
Voltage in the Same Bank......................5-18
CCPD
TOC-5
Altera Corporation