Altera Cyclone V Device Handbook page 338

CV-53001
2013.05.06
Date
December 2012
November 2012
June 2012
Transceiver Architecture in Cyclone V Devices
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Version
• Updated the Word Aligner section.
• Updated the Word Aligner Options and Behaviors
section.
• Updated the Word Aligner in Manual Alignment Mode
section.
• Updated the Programmable Run-Length Violation
Detection section.
• Updated the Rate Match FIFO section.
• Updated the 8B/10B Decoder section.
• Updated the Byte Deserializer section.
• Updated the Byte Ordering in Single-Width Mode
section.
• Updated the Byte Ordering in Double-Width Mode
section.
• Added the Word Aligner-Based Ordering Mode section.
• Added the Manual Ordering Mode section.
• Updated the Receiver Phase Compensation FIFO section.
• Updated the Channel Bonding section.
• Updated the PLL Sharing section.
2012.12.03 Clarified note to Figure 1-6 to indicate only certain
transceiver channels support interfacing to PCIe.
Removed DC-Coupling information from Transmitter
Buffer Features and Capabilities and PMA Receiver Buffer.
2012.11.19 Reorganized content and updated template
1.1 Added in contents of Transceiver Basics for Cyclone V
Devices.
Updated "Architecture Overview", "PMA Architecture"
and "PCS Architecture" sections.
Updated Table 1 11.
Updated Figure 1 36.
Document Revision History
Changes
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