Altera Cyclone V Device Handbook page 335

1-48
Manual Ordering Mode
When the first data byte that matches the byte ordering pattern is found, the byte ordering performs the
following operations:
• If the pattern is not in the LSByte position—byte ordering inserts the appropriate number of pad patterns
to push the byte ordering pattern to the LSByte position and indicates the byte alignment.
• If the pattern is in the LSByte position—byte ordering indicates the byte alignment.
Any byte misalignment found thereafter is ignored unless another rising edge on the rx_syncstatus
signal, indicating resynchronization, is observed.
Manual Ordering Mode
In manual ordering mode, the byte ordering operation is controlled using the rx_enabyteord signal.
A rising edge on the rx_enabyteord signal triggers byte ordering to look for the byte ordering pattern
in the byte-deserialized data.
When the first data byte that matches the byte ordering pattern is found, the byte ordering performs the
following operations:
• If the pattern is not in the LSByte position—byte ordering inserts the appropriate number of pad patterns
to push the byte ordering pattern to the LSByte position and indicates the byte alignment.
• If the pattern is in the LSByte position—byte ordering indicates the byte alignment.
Any byte misalignment found thereafter is ignored unless another rising edge on the rx_enabyteord
signal is observed.
Receiver Phase Compensation FIFO
The receiver phase compensation FIFO is four words deep and interfaces the status and data signals between
the receiver PCS and the FPGA fabric or the PCIe hard IP block.
The low-speed parallel clock feeds the write clock, while the FPGA fabric interface clock feeds the read clock.
The clocks must have 0 ppm difference in frequency or a receiver phase compensation FIFO underrun or
overflow condition may result.
The FIFO supports the following operations:
• Phase compensation mode with various clocking modes on the read clock and write clock
• Registered mode with only one clock cycle of datapath latency
Figure 1-34: Receiver Phase Compensation FIFO
Related Information
Transceiver Clocking in Cyclone V Devices.
Altera Corporation
RX
Phase
Compensation
Datapath to
FIFO
the FPGA Fabric
wr_clk
rx_clkout
Note:
1. These clocks may have been divided by 2 if you used a byte deserializer.
Datapath from the
Last PCS Block Used
rd_clk
Parallel Recovered Clock (1)
tx_clkout (1)
coreclkout (1)
rx_coreclk (1)
Transceiver Architecture in Cyclone V Devices
CV-53001
2013.05.06
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