Phy Interface; Dma Interface; Management Interface; Acceleration - Altera Cyclone V Device Handbook

17-2

PHY Interface

• Preamble and start-of-frame data (SFD) insertion in transmit and deletion in receive paths
• Automatic cyclic redundancy check (CRC) and pad generation controllable on a per-frame basis
• Options for automatic pad/CRC stripping on receive frames
• Programmable frame length supporting standard and jumbo Ethernet frames (with size up to 16 KB)
• Programmable inter-frame gap (IFG), from 40- to 96-bit times in steps of eight
PHY Interface
• Reduced Gigabit Media Independent Interface (RGMII) for 10/100/1000
• Gigabit Media Independent Interface (GMII) through the FPGA fabric
• Serial Gigabit Media Independent Interface (SGMII) supported through the GMII to FPGA fabric
• Media Independent Interface (MII) through the FPGA fabric
• Management Data Input/Output (MDIO) (IEEE 802.3) or I

DMA Interface

• 32-bit interface
• Programmable burst size for optimal bus utilization
• Single-channel mode transmit and receive engines
• Byte-aligned addressing mode for data buffer support
• Dual-buffer (ring) or linked-list (chained) descriptor chaining
• Descriptors can each transfer up to 8 KB of data

Management Interface

• 32-bit host interface to CSR set
• Comprehensive status reporting for normal operation and transfers with errors
• Configurable interrupt options for different operational conditions
• Per-frame transmit/receive complete interrupt control
• Separate status returned for transmission and reception packets

Acceleration

• Transmit and receive checksum offload for transmission control protocol (TCP), user datagram protocol
(UDP), or Internet control message protocol (ICMP) over Internet protocol (IP)

Other Features

• Supports a variety of flexible address filtering modes
• Up to 31 additional 48-bit perfect destination address (DA) filters with masks for each byte
• Up to 31 48-bit source address (SA) comparison check with masks for each byte
• 256-bit hash filter (optional) for multicast and uni-cast DAs
• Option to pass all multicast addressed frames
• Promiscuous mode support to pass all frames without any filtering for network monitoring
• Passes all incoming packets (as per filter) with a status report
Altera Corporation
2
C PHY management interface
Ethernet Media Access Controller
cv_54017
2013.12.30
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