Altera Cyclone V Device Handbook page 298

CV-53001
2013.05.06
Table 1-3: Bit Reversal Feature
Bit Reversal Option
Disabled (default)
Enabled
Transmitter Buffer
Transmitter buffers support the programmable analog settings (differential output voltage and pre-emphasis),
common-mode voltage (TX V
The transmitter buffer includes additional circuitry to improve integrity, such as the programmable
differential output voltage (VOD), programmable three-tap pre-emphasis circuitry, internal termination
circuitry, and PCIe receiver detect capability to support a PCIe configuration.
Modifying programmable values withing transmitter output buffers can be performed by a single reconfig-
uration controller for the entire FPGA, or multiple reconfiguration controllers if desired. Within each
transceiver bank (three-transceiver channels), a maximum of one reconfiguration controller is allowed.
There is only one slave interface to all PLLs and PMAs within each transceiver bank. Therefore, many
transceiver banks can be connected to a single reconfiguration controller, but only one reconfiguration
controller can be connected to the transceiver bank (three-transceiver channels).
Note: A maximum of one reconfiguration controller is allowed per transceiver bank.
Figure 1-9: Transmitter Buffer Block Diagram in Cyclone V Devices
Transceiver Architecture in Cyclone V Devices
Send Feedback
8- or 10-bit Serialization
Factor
LSB to MSB
MSB to LSB
For example:
8-bit—D[7:0] rewired to
D[0:7]
10-bit—D[9:0] rewired to
D[0:9]
), and OCT.
CM
High-speed
Differential
Tx
– +
Transmitter
VCM
Channel
Output Pins
Transmission Bit Order
16- or 20-bit Serialization Factor
LSB to MSB
MSB to LSB
For example:
16-bit—D[15:0] rewired to
D[0:15]
20-bit—D[19:0] rewired to
D[0:19]
Transmitter
Output
Tri-State
From Serializer
Programmable
Pre-Emphasis
and V
OD
Receiver
Detect
1-11
Transmitter Buffer
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