Altera Cyclone V Device Handbook page 802

16-6
Operating States
Executing
The thread has a valid PC and therefore the DMAC includes the thread when it arbitrates. The thread can
then change to one of the following states under the following conditions:
• Stopped When the DMA manager thread executes DMAEND
• Cache miss When the instruction cache does not contain the next instruction for either the DMA
manager thread or the DMA channel thread
• Updating PC When the DMAC calculates the address of the next access in the cache
• Waiting for event When a thread executes DMAWFE
• At barrier When a DMA channel thread either:
• Executes DMARMB, DMAWMB, or DMAFLUSHP
• Updates control registers that affect alignment during a DMA Cycle
• Waiting for peripheral When a DMA channel thread executes DMAWFP
• Killing When a DMA channel thread executes DMAKILL
• Faulting completing For a DMA channel thread when either:
• The thread executes an undefined or invalid instruction
• An AXI error occurs during an instruction fetch or data transfer
• Faulting For the DMA manager thread when either:
• The thread executes an undefined or invalid instruction
• An AXI error occurs during an instruction fetch
For a DMA channel thread when a watchdog timeout abort occurs.
• Completing When a DMA channel thread executes DMAEND
Cache Miss
The thread is stalled and the DMAC is performing a cache line fill. After it completes the cache fill, the thread
returns to the Executing state.
Updating PC
The DMAC is calculating the address of the next access in the cache. After it calculates the PC, the thread
returns to the Executing state.
Waiting For Event
The thread is stalled and is waiting for the DMAC to execute DMASEV using the corresponding event number.
After the corresponding event occurs, the thread returns to the Executing state.
At Barrier
A DMA channel thread is stalled and the DMAC is waiting for transactions on the AXI to complete. After
the AXI transactions complete, the thread returns to the Executing state.
Waiting For Peripheral
A DMA channel thread is stalled and the DMAC is waiting for the peripheral to provide the requested data.
After the peripheral provides the data, the thread returns to the Executing state.
Altera Corporation
cv_54016
2013.12.30
DMA Controller
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