Altera Cyclone V Device Handbook page 552

6-6
Interactive Debugging Features
®
• Jazelle DBX Extensions for byte-code dynamic compiler support
• The Cortex-A9 processor architecture supports the following instruction sets:
• The ARMv7-A performance-optimized instruction set
• The memory-optimized Thumb
• Improves energy efficiency
• 31% smaller memory footprint
• 38% faster than the original Thumb instruction set
• The Thumb instruction set supported for legacy applications
• Each processor core in the Altera HPS includes a memory management unit (MMU) to support the
memory management requirements of common modern operating systems.
The Cortex-A9 processors are designated CPU0 and CPU1.
Detailed documentation of ARM Cortex-A9 series processors is available on the ARM website
(infocenter.arm.com).
Related Information
ARM Infocenter (www.infocenter.arm.com)
Interactive Debugging Features
Each Cortex-A9 processor has built-in debugging capabilities, including the following features:
• Six hardware breakpoints, including two with Context ID comparison capability
• Four watchpoints
The interactive debugging features can be controlled by external JTAG tools or by processor-based monitor
code.
For more information about the interactive debugging system, refer to the Debug chapter of the Cortex-A9
Technical Reference Manual, available on the ARM website (infocenter.arm.com).
Related Information
ARM Infocenter (www.infocenter.arm.com)
L1 Caches
Cache memory that is closely coupled with an associated processor is called level 1, or L1 cache. Each Cortex-
A9 processor has two independent 32 KB L1 caches one for instructions and one for data allowing
simultaneous instruction fetches and data access.
Each L1 cache is four-way set associative, with 32 bytes per line, and supports parity checking.
Preload Engine
The preload engine (PLE) is a hardware block that enables the L2 cache to preload selected regions of memory.
The PLE signals the L2 cache when a cache line will be needed in the L2 cache, by making the processor data
master port start fetching the data. The processor data master does not complete the fetch or return the data
to the processor. However, the L2 cache can then proceed to load the cache line. The data is only loaded to
the L2 cache, not to the L1 cache or processor registers.
Altera Corporation
®
-2 mixed instruction set
Cortex-A9 Microprocessor Unit Subsystem
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2013.12.30