Rate Match Fifo In Custom Configuration - Altera Cyclone V Device Handbook

CV-53005
2013.05.06
Figure 5-6: Configuration Options for Custom Double-Width Mode (20-bit PMA PCS Interface Width)

Rate Match FIFO in Custom Configuration

In a custom configuration, the 20-bit pattern for the rate match FIFO is user-defined. The FIFO operates
by looking for the 10-bit control pattern followed by the 10-bit skip pattern in the data, after the word aligner
restores the word boundary. After finding the pattern, the FIFO performs a skip pattern insertion or deletion
to ensure that the FIFO does not underflow or overflow a given parts per million (ppm) difference between
the clocks.
The rate match FIFO operation requires 8B/10B-coded data.
Rate Match FIFO Behaviors in Custom Single-Width Mode
The different operations available in custom single-width mode for the rate match FIFO are symbol insertion,
symbol deletion, full condition, and empty condition.
Table 5-2: Rate Match FIFO Behaviors in Custom Single-Width Mode (10-bit PMA PCS Interface Width)
Symbol Insertion
Symbol Deletion
Full Condition
Empty Condition
Transceiver Custom Configurations in Cyclone V Devices
Send Feedback
Word Aligner (Pattern Length)
8B/10B Encoder/Decoder
Rate Match FIFO
Byte SERDES
Disabled
FPGA Fabric–Transceiver
Interface Width
Data Rate (Gbps) GX/SX= 3.125
GT/ST= 3.2768
Operation
Rate Match FIFO in Custom Configuration
Manual Alignment
or Bit-Slip
Disabled Enabled
Disabled Disabled
Enabled Disabled Enabled
20-Bit 40-Bit 16-Bit
GX/SX= 3.125 GX/SX= 3.125
GT/ST= 5 GT/ST= 3.2768
Inserts a maximum of four skip patterns in a cluster,
only if there are no more than five skip patterns in the
cluster after the symbol insertion.
Deletes a maximum of four skip patterns in a cluster,
only if there is one skip pattern left in the cluster after
the symbol deletion.
Deletes the data byte that causes the FIFO to go full.
Inserts a /K30.7/ (9'h1FE) after the data byte that
caused the FIFO to go empty.
32-Bit
GX/SX= 3.125
GT/ST= 5
Behavior
5-5
Altera Corporation