Altera Cyclone V Device Handbook page 690

11-12
Abort During Internal DMA Transfer
1. The internal DMA controller performs four accesses to fetch a descriptor.
2. The DMA controller stores the descriptor information internally. If it is the first descriptor, the controller
issues a FIFO buffer reset and waits until the reset is complete.
3. The internal DMA controller checks each bit of the descriptor for the correctness. If bit mismatches are
found, the appropriate error bit is set to 1 and the descriptor is closed by setting the OWN bit in the DES0
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field to 1.
The rintsts register indicates one of the following conditions:
• Response timeout
• Response CRC error
• Data receive timeout
• Response error
4. The DMA waits for the RX watermark to be reached before writing data to system memory, or the TX
watermark to be reached before reading data from system memory. The RX watermark represents the
number of bytes to be locally stored in the FIFO buffer before the DMA writes to memory. The TX
watermark represents the number of free bytes in the local FIFO buffer before the DMA reads data from
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memory.
5. If the value of the programmable burst length (PBL) field is larger than the remaining amount of data in
the buffer, single transfers are initiated. If dual buffers are being used, and the second buffer contains no
data (buffer size = 0), the buffer is skipped and the descriptor is closed.
6. The OWN bit in descriptor is set to 0 by the internal DMA controller after the data transfer for one
descriptor is completed. If the transfer spans more than one descriptor, the DMA controller fetches the
next descriptor. If the transfer ends with the current descriptor, the internal DMA controller goes to idle
state after setting the ri bit or the ti bit of the idsts register. Depending on the descriptor structure
(dual buffer or chained), the appropriate starting address of descriptor is loaded. If it is the second data
buffer of dual buffer descriptor, the descriptor is not fetched again.
Abort During Internal DMA Transfer
If the host issues an SD/SDIO STOP_TRANSMISSION command (CMD12) to the card while data transfer
is in progress, the internal DMA controller closes the present descriptor after completing the data transfer
until a Data Transfer Over (DTO) interrupt is asserted. Once a STOP_TRANSMISSION command is issued,
the DMA controller performs single burst transfers.
• For a card write operation, the internal DMA controller keeps writing data to the FIFO buffer after
fetching it from the system memory until a DTO interrupt is asserted. This is done to keep the card clock
running so that the STOP_TRANSMISSION command is reliably sent to the card.
• For a card read operation, the internal DMA controller keeps reading data from the FIFO buffer and
writes to the system memory until a DTO interrupt is generated. This is required because DTO interrupt
is not generated until and unless all the FIFO buffer data is emptied.
Note: For a card write abort, only the current descriptor during which a STOP_TRANSMISSION command
is issued is closed by the internal DMA controller. The remaining unread descriptors are not closed
by the internal DMA controller.
Note: For a card read abort, the internal DMA controller reads the data out of the FIFO buffer and writes
them to the corresponding descriptor data buffers. The remaining unread descriptors are not closed.
Altera Corporation
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2013.12.30
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